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| PRELIMINARY Integrated Circuit Systems, Inc. ICS87366 1-TO-6, DIFFERENTIAL TO 3.3V LVPECL CLOCK GENERATOR W/FORWARD ERROR CORRECTION FEATURES * 6 differential LVPECL outputs * 1 differential CLK/nCLK input pair * CLK/nCLK pair can accept the following differential input levels: LVPECL, LVDS, LVHSTL, HCSL, SSTL * Output frequency: FEC_SEL = 0, 159.375MHz FEC_SEL = 1, 164.355MHz * Cycle-to-cycle jitter: FEC_SEL = 0, 15ps (typical) FEC_SEL = 1, 20ps (typical) * Full 3.3V or 3.3V core/2.5V output supply voltage * 0C to 70C ambient operating temperature GENERAL DESCRIPTION The ICS87366 is a 1-to-6, Differential to 3.3V LVPECL Clock Generator and a member of the HiPerClockSTM HiPerClockSTM family of High Performance Clock Solutions from ICS. The ICS87366 can multiply the reference clock times 3 or multiply times 3 * 66/64 thereby applying an FEC rate to the reference clock. The ICS87366 is an ideal device in any application requiring x3 multiplication with an 66/64 FEC option while maintaining low jitter. Common applications may include networking and storage area networks. ,&6 BLOCK DIAGRAM Q0 nQ0 PLL_SEL Q1 nQ1 Q2 0 0 1 Input Divider 1 PLL Output Divider PIN ASSIGNMENT Q0 nQ0 Q1 nQ1 Q2 nQ2 Q3 nQ3 Q4 nQ4 Q5 nQ5 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 VCCO FEC_SEL nc MR CLK nCLK VEE VCCA VCC PLL_SEL VEE VCCO CLK nCLK nQ2 Q3 nQ3 Q4 nQ4 Q5 0 1 Feedback Divider nQ5 ICS87366 24-Lead, 300-MIL SOIC 7.5mm x 15.33mm x 2.3mm body package M Package Top View FEC_SEL MR The Preliminary Information presented herein represents a product in prototyping or pre-production. The noted characteristics are based on initial product characterization. Integrated Circuit Systems, Incorporated (ICS) reserves the right to change any circuitry or specifications without notice. 87366AM www.icst.com/products/hiperclocks.html 1 REV. A SEPTEMBER 9, 2003 PRELIMINARY Integrated Circuit Systems, Inc. ICS87366 1-TO-6, DIFFERENTIAL TO 3.3V LVPECL CLOCK GENERATOR W/FORWARD ERROR CORRECTION Type Output Output Output Output Output Output Power Power Input Power Power Input Input Input Unused Input Pullup Pullup Description Differential output pair. LVPECL interface levels. Differential output pair. LVPECL interface levels. Differential output pair. LVPECL interface levels. Differential output pair. LVPECL interface levels. Differential output pair. LVPECL interface levels. Differential output pair. LVPECL interface levels. Output supply pins. Negative supply pins. Selects between the PLL and CLK, nCLK as the input to the dividers. When HIGH, selects PLL. When LOW, selects CLK, nCLK. LVCMOS / LVTTL interface levels. Core supply pin. Analog supply pin. Pullup/ Inver ting differential clock input. VCC/2 defaults when left floating. Pulldown Pulldown Non-inver ting differential clock input. Active High Master Reset. When logic HIGH, the internal dividers are reset causing the true outputs Qx to go low and the inver ted outputs Pulldown nQx to go high. When logic LOW, the internal dividers and the outputs are enabled. LVCMOS / LVTTL interface levels. No connect. TABLE 1. PIN DESCRIPTIONS Number 1, 2 3, 4 5, 6 7, 8 9, 10 11, 12 13, 24 14, 18 15 16 17 19 20 21 22 23 Name Q0, nQ0 Q1, nQ1 Q2, nQ2 Q3, nQ3 Q4, nQ4 Q5, nQ5 VCCO VEE PLL_SEL VCC VCCA nCLK CLK MR nc FEC_SEL Select pin controls the Feedback Divide value. LVCMOS / LVTTL interface levels. NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values. TABLE 2. PIN CHARACTERISTICS Symbol CIN RPULLUP RPULLDOWN Parameter Input Capacitance Input Pullup Resistor Input Pulldown Resistor Test Conditions Minimum Typical 4 51 51 Maximum Units pF KW KW TABLE 3. FUNCTION TABLE Inputs MR 1 0 0 FEC_SEL X 0 1 Multiplier Reset: Qx = LOW, nQx = HIGH 3 3 x 33/32 87366AM www.icst.com/products/hiperclocks.html 2 REV. A SEPTEMBER 9, 2003 PRELIMINARY Integrated Circuit Systems, Inc. ICS87366 1-TO-6, DIFFERENTIAL TO 3.3V LVPECL CLOCK GENERATOR W/FORWARD ERROR CORRECTION 4.6V -0.5V to VCC + 0.5V 50mA 100mA 50C/W (0 lfpm) -65C to 150C NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. ABSOLUTE MAXIMUM RATINGS Supply Voltage, VCC Inputs, VI Outputs, IO Continuous Current Surge Current Package Thermal Impedance, JA Storage Temperature, TSTG TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VCC = VCCA = 3.3V5%, VCCO = 3.3V5% OR 2.5V5%, TA = 0C TO 70C Symbol VCC VCCA VCCO VCCO I EE ICCA Parameter Core Supply Voltage Analog Supply Voltage Output Supply Voltage Output Supply Voltage Power Supply Current Analog Supply Current Test Conditions Minimum 3.135 3.135 3.135 2.375 Typical 3.3 3.3 3.3 2.5 TBD TBD Maximum 3.465 3.465 3.465 2.625 Units V V V V mA mA TABLE 4B. LVCMOS / LVTTL DC CHARACTERISTICS, VCC = VCCA = 3.3V5%, VCCO = 3.3V5% OR 2.5V5%, TA = 0C TO 70C Symbol VIH VIL IIH IIL Parameter Input High Voltage Input Low Voltage Input High Current Input Low Current PLL_SEL, MR, FEC_SEL PLL_SEL, MR, FEC_SEL MR PLL_SEL, FEC_SEL MR PLL_SEL, FEC_SEL Test Conditions Minimum 2 -0.3 VCC = VIN = 3.465V VCC = VIN = 3.465V VCC = 3.465V, VIN = 0V VCC = 3.465V, VIN = 0V -5 -150 Typical Maximum VCC + 0.3 0.8 150 5 Units V V A A A A TABLE 4C. DIFFERENTIAL DC CHARACTERISTICS, VCC = VCCA = 3.3V5%, VCCO = 3.3V5% OR 2.5V5%, TA = 0C TO 70C Symbol IIH IIL VPP Parameter Input High Current Input Low Current CLK nCLK CLK nCLK Test Conditions VCC = VIN = 3.465V VCC = VIN = 3.465V VCC = 3.465V, VIN = 0V VCC = 3.465V, VIN = 0V -5 -150 0.15 1.0 VCC - 0.85 Minimum Typical Maximum 150 150 Units A A A A V V Peak-to-Peak Voltage Common Mode Input Voltage; NOTE 1, 2 VEE + 0.5 VCMR NOTE 1: Common mode input voltage is defined as VIH. NOTE 2: For single ended applications, the maximum input voltage for CLK, nCLK is VCC + 0.3V. 87366AM www.icst.com/products/hiperclocks.html 3 REV. A SEPTEMBER 9, 2003 PRELIMINARY Integrated Circuit Systems, Inc. ICS87366 1-TO-6, DIFFERENTIAL TO 3.3V LVPECL CLOCK GENERATOR W/FORWARD ERROR CORRECTION Test Conditions Minimum VCCO - 1.4 VCCO - 2.0 0.6 Typical Maximum VCCO - 1.0 VCCO - 1.7 1.0 Units V V A TABLE 4D. LVPECL DC CHARACTERISTICS, VCC = VCCA = 3.3V5%, VCCO = 3.3V5% OR 2.5V5%, TA = 0C TO 70C Symbol VOH VOL VSWING Parameter Output High Voltage; NOTE 1 Output Low Voltage; NOTE 1 Peak-to-Peak Output Voltage Swing NOTE 1: Outputs terminated with 50W to VCCO - 2V. TABLE 5A. AC CHARACTERISTICS, VCC = VCCA = VCCO = 3.3V5%, TA = 0C TO 70C Symbol Parameter FOUT Output Frequency Cycle-to-Cycle Jitter ; NOTE 3 Output Skew; NOTE 1, 3 Par t-to-Par t Skew, NOTE 2 Output Rise/Fall Time Output Duty Cycle 20% to 80% 200 50 FEC_SEL = 0 FEC_SEL = 1 Test Conditions Minimum 159.375 15 20 TBD TBD 700 Typical Maximum 164.355 Units MHz ps ps ps ps ps % tjit(cc) tsk(o) tsk(pp) tR / tF odc PLL Lock Time 1 ms tLOCK NOTE 1: Defined as skew between outputs on different devices operating at the same supply voltages and with equal load conditions. Using the same type of inputs on each device, the outputs are measured at the differential cross points. NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at VCCO/2. NOTE 3: This parameter is defined in accordance with JEDEC Standard 65. TABLE 5B. AC CHARACTERISTICS, VCC = VCCA = 3.3V5%, VCCO = 2.5V5%, TA = 0C TO 70C Symbol Parameter FOUT Output Frequency Cycle-to-Cycle Jitter ; NOTE 3 Output Skew; NOTE 1, 3 Par t-to-Par t Skew, NOTE 2 Output Rise/Fall Time Output Duty Cycle 20% to 80% 200 50 FEC_SEL = 0 FEC_SEL = 1 Test Conditions Minimum 159.375 TBD TBD TBD TBD 700 Typical Maximum 164.355 Units MHz ps ps ps ps ps % tjit(cc) tsk(o) tsk(pp) tR / tF odc tLOCK PLL Lock Time 1 ms NOTE 1: Defined as skew between outputs on different devices operating at the same supply voltages and with equal load conditions. Using the same type of inputs on each device, the outputs are measured at the differential cross points. NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at VCCO/2. NOTE 3: This parameter is defined in accordance with JEDEC Standard 65. 87366AM www.icst.com/products/hiperclocks.html 4 REV. A SEPTEMBER 9, 2003 PRELIMINARY Integrated Circuit Systems, Inc. ICS87366 1-TO-6, DIFFERENTIAL TO 3.3V LVPECL CLOCK GENERATOR W/FORWARD ERROR CORRECTION PARAMETER MEASUREMENT INFORMATION 2V 2V 2.8V0.04V Qx V CC , VCCA, VCCO SCOPE V CC , VCCA, VCCO Qx SCOPE LVPECL nQx LVPECL VEE nQx VEE -1.3V 0.165V -0.5V 0.125V 3.3V CORE/3.3V OUTPUT LOAD AC TEST CIRCUIT VCC 3.3V CORE/2.5V OUTPUT LOAD AC TEST CIRCUIT nQx nCLK V CLK Qy tsk(o) PP Qx Cross Points V CMR nQy VEE DIFFERENTIAL INPUT LEVEL PART 1 nQx Qx PART 2 nQy Qy tsk(o) OUTPUT SKEW nQ0:nQ5 Q0:Q5 tcycle n tjit(cc) = tcycle n -tcycle n+1 1000 Cycles PART-TO-PART SKEW CYCLE-TO-CYCLE JITTER nQ0:nQ5 80% Clock Outputs 80% VSW I N G 20% tR tF odc = Q0:Q5 Pulse Width t PERIOD 20% t PW t PERIOD OUTPUT RISE/FALL TIME 87366AM OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD www.icst.com/products/hiperclocks.html 5 REV. A SEPTEMBER 9, 2003 tcycle n+1 PRELIMINARY Integrated Circuit Systems, Inc. ICS87366 1-TO-6, DIFFERENTIAL TO 3.3V LVPECL CLOCK GENERATOR W/FORWARD ERROR CORRECTION APPLICATION INFORMATION POWER SUPPLY FILTERING TECHNIQUES As in any high speed analog circuitry, the power supply pins are vulnerable to random noise. The ICS87366 provides separate power supplies to isolate any high switching noise from the outputs to the internal PLL. VCC, VCCA and VCCO should be individually connected to the power supply plane through vias, and bypass capacitors should be used for each pin. To achieve optimum jitter performance, power supply isolation is required. Figure 1 illustrates how a 10 resistor along with a 10F and a .01F bypass capacitor should be connected to each VCCA pin. 3.3V VCC .01F V CCA .01F 10 F 10 FIGURE 1. POWER SUPPLY FILTERING TERMINATION FOR LVPECL OUTPUTS The clock layout topology shown below is a typical termination for LVPECL outputs. The two different layouts mentioned are recommended only as guidelines. FOUT and nFOUT are low impedance follower outputs that generate ECL/LVPECL compatible outputs. Therefore, terminating resistors (DC current path to ground) or current sources must be used for functionality. These outputs are designed to drive 50 transmission lines. Matched impedance techniques should be used to maximize operating frequency and minimize signal distortion. Figures 2A and 2B show two different layouts which are recommended only as guidelines. Other suitable clock layouts may exist and it would be recommended that the board designers simulate to guarantee compatibility across all printed circuit and clock component process variations. 3.3V Zo = 50 FOUT FIN 125 Zo = 50 FOUT 50 50 VCC - 2V RTT 125 Zo = 50 FIN RTT = 1 Zo (VOH + VOL / VCC - 2) - 2 Zo = 50 84 84 FIGURE 2A. LVPECL OUTPUT TERMINATION FIGURE 2B. LVPECL OUTPUT TERMINATION 87366AM www.icst.com/products/hiperclocks.html 6 REV. A SEPTEMBER 9, 2003 PRELIMINARY Integrated Circuit Systems, Inc. DIFFERENTIAL CLOCK INPUT INTERFACE The CLK /nCLK accepts LVDS, LVPECL, LVHSTL, SSTL, HCSL and other differential signals. Both VSWING and VOH must meet the VPP and VCMR input requirements. Figures 3A to 3D show interface examples for the HiPerClockS CLK/nCLK input driven by the most common driver types. The input interfaces suggested ICS87366 1-TO-6, DIFFERENTIAL TO 3.3V LVPECL CLOCK GENERATOR W/FORWARD ERROR CORRECTION here are examples only. Please consult with the vendor of the driver component to confirm the driver termination requirements. For example in Figure 3A, the input termination applies for ICS HiPerClockS LVHSTL drivers. If you are using an LVHSTL driver from another vendor, use their termination recommendation. 3.3V 3.3V 3.3V 1.8V Zo = 50 Ohm Zo = 50 Ohm CLK Zo = 50 Ohm nCLK LVHSTL ICS HiPerClockS LVHSTL Driver R1 50 R2 50 R3 50 LVPECL Zo = 50 Ohm CLK nCLK HiPerClockS Input HiPerClockS Input R1 50 R2 50 FIGURE 3A. HIPERCLOCKS CLK/NCLK INPUT DRIVEN ICS HIPERCLOCKS LVHSTL DRIVER BY FIGURE 3B. HIPERCLOCKS CLK/NCLK INPUT DRIVEN 3.3V LVPECL DRIVER BY 3.3V 3.3V 3.3V R3 125 Zo = 50 Ohm CLK Zo = 50 Ohm nCLK LVPECL R1 84 R2 84 HiPerClockS Input R4 125 3.3V 3.3V LVDS_Driv er Zo = 50 Ohm CLK R1 100 Zo = 50 Ohm nCLK Receiv er FIGURE 3C. HIPERCLOCKS CLK/NCLK INPUT DRIVEN 3.3V LVPECL DRIVER BY FIGURE 3D. HIPERCLOCKS CLK/NCLK INPUT DRIVEN 3.3V LVDS DRIVER BY 87366AM www.icst.com/products/hiperclocks.html 7 REV. A SEPTEMBER 9, 2003 PRELIMINARY Integrated Circuit Systems, Inc. ICS87366 1-TO-6, DIFFERENTIAL TO 3.3V LVPECL CLOCK GENERATOR W/FORWARD ERROR CORRECTION RELIABILITY INFORMATION TABLE 6. JAVS. AIR FLOW TABLE JA by Velocity (Linear Feet per Minute) 0 Multi-Layer PCB, JEDEC Standard Test Boards 50C/W 200 43C/W 500 38C/W NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs. TRANSISTOR COUNT The transistor count for ICS87366 is: 3069 87366AM www.icst.com/products/hiperclocks.html 8 REV. A SEPTEMBER 9, 2003 PRELIMINARY Integrated Circuit Systems, Inc. ICS87366 1-TO-6, DIFFERENTIAL TO 3.3V LVPECL CLOCK GENERATOR W/FORWARD ERROR CORRECTION PACKAGE OUTLINE - M SUFFIX TABLE 7. PACKAGE DIMENSIONS SYMBOL N A A1 A2 B C D E e H h L 10.00 0.25 0.40 0 -0.10 2.05 0.33 0.18 15.20 7.40 1.27 BASIC 10.65 0.75 1.27 8 Millimeters Minimum 24 2.65 -2.55 0.51 0.32 15.85 7.60 Maximum a Reference Document: JEDEC Publication 95, MS-013, MO-119 87366AM www.icst.com/products/hiperclocks.html 9 REV. A SEPTEMBER 9, 2003 PRELIMINARY Integrated Circuit Systems, Inc. ICS87366 1-TO-6, DIFFERENTIAL TO 3.3V LVPECL CLOCK GENERATOR W/FORWARD ERROR CORRECTION Marking ICS87366AM ICS87366AM Package 24 Lead SOIC 24 Lead SOIC on Tape and Reel Count 30 per tube 1000 Temperature 0C to 70C 0C to 70C TABLE 8. ORDERING INFORMATION Part/Order Number ICS87366AM ICS87366AMT While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices or critical medical instruments. 87366AM www.icst.com/products/hiperclocks.html 10 REV. A SEPTEMBER 9, 2003 |
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